Electronic design automation (EDA) technology is becoming increasingly sophisticated, allowing circuit designers to create highly complex integrated circuits with greater functionality and better performance.
The place and route (P&R) stage of circuit design typically involves multiple steps. The typical P&R tool first partitions design data (e.g., netlist) into a top level design and many block-level designs, outputting block-level circuit descriptions as Design Exchange Format (DEF) files. Boundary/timing constraints of the blocks are generated in standard formats such as Synopsis Design Constraints (SDC). Individual blocks are then flattened and processed by a block level P&R engine designed to process flat, non-hierarchical circuit blocks. The timing of individual blocks is obtained based on analysis by the block level engine. A block may be assigned a certain timing budget such as maximum/minimum input/output delays. The block-level P&R engine would find the optimal placement and routing implementation for the block designs, while ensuring all block-level timing budgets are met. After the block-level P&R, the block designs are translated into an abstract representation with necessary timing and physical boundary information, before they are incorporated into the top level design. If any of the block-level I/O budget is not met, the corresponding inter-block timing path may not reach closure. In such case, the blocks involved in the critical timing path will need to be re-budgeted. New SDC files will need to be regenerated and block-level P&R will need to be refined. This iterative process goes on until all block-level and inter-block timings are closed.
A number of issues exist in the typical P&R process. Since the process is broken down into several steps involving different data representations, data management is complex, expensive, and error-prone. The top level and the block level are processed using separate engines, which can lead to timing correlation and tool compatibility problems. Since the top level designers and block level designers typically only have access to data for their respective levels, the assignment and modification of timing budgets tend to be inflexible. Also, the process usually goes through multiple iterations that require extensive coordination between block level and top level designers. For example, the designers usually have to exchange modified data by exporting and importing different files and merge modified data into the overall design. As a result, the turn-around time required to achieve timing closure is often lengthy.